About
Registration
Conference
Technical Program
Exhibits
News & Press
Travel
Advisory Committee
Contact Information
History
SC07 Committees
Sponsoring Societies
Steering Committee
Overview
Overview
Schedule
Last-Minute Schedule Updates and Changes
My Itinerary
Keynote
Broader Engagement
Cluster Challenge
Education
Important Dates
SCinet
Student Volunteers
SC Fellowship
Overview
Awards
BOFs
Challenges
Disruptive Technologies
Doctoral Showcase
Keynote & Invited Speakers
Masterworks
Panels
Papers
Posters
Tutorials
Workshops
Overview
Exhibitor Forum
Exhibitor Information
Floor Plan
Industry Exhibits
Research Exhibits
Exhibitor List
Overview
Press Releases
Newsletters
For Media Professionals
Overview
Conference Hotels
About Reno
Maps and Directions
Conference Shuttle Schedule
SCHEDULE: NOV 10-16, 2007
Warning: It appears you do not have Javascript enabled.
If so, you will have trouble creating and viewing your itinerary information.
Optical Printed Circuit Board Technology and 200+200Gbps Transceiver
Session:
Disruptive Technology Exhibits
Event Type:
Disruptive Technology Exhibit
Time:
10:00am - 6:00pm
Author(s)
:
Clint Schow, Fuad Doany, Jeffrey Kash, Marc Taubenblatt
Location:
Exhibit Hall 1B
Abstract:
IBM Research has developed an Optical Printed Circuit Board technology consisting of chip-like optical transceivers (currently supporting 16+16 optical channels at 12.5Gbps each) and polymer waveguides on circuit cards. Our technology is disruptive in that it would replace today’s high cost optical modules based on glass fiber technology with mass manufacturable "optical printed circuit boards." for short backplane and card level links. Although polymer based waveguides have higher losses than glass fiber technology, the ability to use lithographic processes to mass produce this technology coupled with the use of chip like optical components will allow a low cost solution for this ultra-short interconnect application. We are working to develop a supplier ecosystem to mature this technology in the next 5 to 7 years. As microprocessors become more capable through multi-core architectures, the technology bottleneck for HPC is shifting to the interconnect fabric, requiring immense low power BW at low cost.
Chair/Author Details:
Clint Schow
IBM
Fuad Doany
IBM
Jeffrey Kash
IBM
Marc Taubenblatt
IBM
Home
|
About
|
Contact Us
|
Registration